diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/conf/files.sgimips ./conf/files.sgimips --- /cvs/netbsd/src/sys/arch/sgimips/conf/files.sgimips 2003-09-28 16:41:13.000000000 +0900 +++ ./conf/files.sgimips 2003-09-28 20:38:59.000000000 +0900 @@ -24,14 +24,14 @@ attach crime at mainbus file arch/sgimips/dev/crime.c crime -device mace {[offset = -1], [intr = -1]} +device mace {[offset = -1], [intr = -1], [intrmask = 0] } attach mace at mainbus file arch/sgimips/dev/mace.c mace attach com at mace with com_mace file arch/sgimips/dev/com_mace.c com_mace -device lpt # XXX +device lpt attach lpt at mace with lpt_mace file arch/sgimips/dev/lpt_mace.c lpt_mace file dev/ic/lpt.c lpt_mace @@ -39,7 +39,7 @@ attach pckbc at mace with pckbc_mace file arch/sgimips/dev/pckbc_mace.c pckbc_mace -device mcclock # XXX +device mcclock attach mcclock at mace with mcclock_mace file arch/sgimips/dev/mcclock_mace.c mcclock_mace @@ -47,6 +47,10 @@ attach mec at mace file arch/sgimips/dev/if_mec.c mec +device macau: audiobus, ad1848, auconv +attach macau at mace with macau +file arch/sgimips/dev/macau_mace.c macau + device macepci: pcibus attach macepci at mace file arch/sgimips/pci/macepci.c macepci diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/conf/majors.sgimips ./conf/majors.sgimips --- /cvs/netbsd/src/sys/arch/sgimips/conf/majors.sgimips 2003-09-28 16:41:13.000000000 +0900 +++ ./conf/majors.sgimips 2003-09-28 20:40:28.000000000 +0900 @@ -68,3 +68,4 @@ device-major ksyms char 77 ksyms device-major pf char 78 pf device-major crypto char 79 opencrypto +device-major lpt char 80 lpt diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/com_mace.c ./dev/com_mace.c --- /cvs/netbsd/src/sys/arch/sgimips/dev/com_mace.c 2003-08-01 01:51:52.000000000 +0900 +++ ./dev/com_mace.c 2003-09-28 20:38:59.000000000 +0900 @@ -94,8 +94,8 @@ struct mace_attach_args *maa = aux; sc->sc_iot = maa->maa_st; - sc->sc_ioh = maa->maa_sh; - sc->sc_iobase = maa->maa_sh; + sc->sc_ioh = maa->maa_sh + maa->maa_offset; + sc->sc_iobase = sc->sc_ioh; sc->sc_frequency = COM_FREQ; @@ -104,8 +104,7 @@ com_attach_subr(sc); delay(10000); - mace_intr_establish(4, IPL_TTY, comintr, sc); - /*mace_intr_establish(maa->maa_intr, IPL_TTY, comintr, sc);*/ + mace_intr_establish(maa->maa_intr, maa->maa_intrmask, comintr, sc); return; } diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/crime.c ./dev/crime.c --- /cvs/netbsd/src/sys/arch/sgimips/dev/crime.c 2003-08-01 01:51:52.000000000 +0900 +++ ./dev/crime.c 2003-09-28 22:15:16.000000000 +0900 @@ -50,19 +50,17 @@ #include #include -#include - -#include +#include #include #include "locators.h" static int crime_match(struct device *, struct cfdata *, void *); static void crime_attach(struct device *, struct device *, void *); -void * crime_intr_establish(int, int, int, int (*)(void *), void *); -void crime_intr(u_int); -CFATTACH_DECL(crime, sizeof(struct device), +struct crime_softc *crime_sc; /* only one per machine, okay to be global */ + +CFATTACH_DECL(crime, sizeof(struct crime_softc), crime_match, crime_attach, NULL, NULL); #define CRIME_NINTR 32 /* XXX */ @@ -94,10 +92,19 @@ struct device *self; void *aux; { + struct crime_softc *sc = (struct crime_softc *)self; struct mainbus_attach_args *ma = aux; u_int64_t crm_id; - crm_id = bus_space_read_8(ma->ma_iot, ma->ma_ioh, 0); + crime_sc = sc; + + sc->iot = SGIMIPS_BUS_SPACE_HPC; + + if (bus_space_map(sc->iot, ma->ma_addr, NULL, + BUS_SPACE_MAP_LINEAR, &sc->ioh)) + panic("crime_attach: can't map I/O space"); + + crm_id = bus_space_read_8(sc->iot, sc->ioh, CRIME_REV); aprint_naive(": system ASIC"); @@ -126,13 +133,18 @@ aprint_normal(" (CRIME_ID: %llx)\n", crm_id); - /* All interrupts off. Turned on as we register devices */ - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTSTAT) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_SOFTINT) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_HARDINT) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_STATUS) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK) = 0; + /* Turn on memory error and crime error interrupts. + All others turned on as devices are registered. */ + bus_space_write_8(sc->iot, sc->ioh, CRIME_INTMASK, + CRIME_INT_MEMERR | + CRIME_INT_CRMERR | + CRIME_INT_VICE | + CRIME_INT_VID_OUT | + CRIME_INT_VID_IN2 | + CRIME_INT_VID_IN1); + bus_space_write_8(sc->iot, sc->ioh, CRIME_INTSTAT, 0); + bus_space_write_8(sc->iot, sc->ioh, CRIME_SOFTINT, 0); + bus_space_write_8(sc->iot, sc->ioh, CRIME_HARDINT, 0); } /* @@ -153,6 +165,8 @@ crime[irq].func = func; crime[irq].arg = arg; + crime_intr_mask(irq); + return (void *)&crime[irq]; } @@ -168,3 +182,12 @@ } } +void +crime_intr_mask(unsigned int intr) +{ + u_int64_t mask; + + mask = bus_space_read_8(crime_sc->iot, crime_sc->ioh, CRIME_INTMASK); + mask |= (1 << intr); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, CRIME_INTMASK, mask); +} diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/crimereg.h ./dev/crimereg.h --- /cvs/netbsd/src/sys/arch/sgimips/dev/crimereg.h 2003-01-12 10:01:50.000000000 +0900 +++ ./dev/crimereg.h 2003-09-28 21:06:19.000000000 +0900 @@ -36,10 +36,8 @@ * O2 CRIME register definitions */ -#define CRIME_BASE 0x14000000 /* all registers 64-bit access */ - /* Offset 0x00 -- revision register */ -#define CRIME_REV (CRIME_BASE+0x000) +#define CRIME_REV 0x00 #define CRIME_ID_IDBITS 0xf0 #define CRIME_ID_IDSHIFT 4 #define CRIME_ID_REV 0x0f @@ -49,7 +47,7 @@ #define CRIME_REV_14 0x14 /* offset 0x08 -- control register. Only lower 14 bits are valid*/ -#define CRIME_CONTROL (CRIME_BASE+0x008) +#define CRIME_CONTROL 0x08 #define CRIME_CONTROL_TRITON_SYSADC 0x2000 #define CRIME_CONTROL_CRIME_SYSADC 0x1000 #define CRIME_CONTROL_HARD_RESET 0x0800 @@ -83,7 +81,7 @@ /* Offset 0x010 -- interrupt status register. All 32 bits valid */ -#define CRIME_INTSTAT (CRIME_BASE+0x010) +#define CRIME_INTSTAT 0x10 #define CRIME_INT_VICE 0x80000000 #define CRIME_INT_SOFT2 0x40000000 /* Also CPU_SysCorErr */ #define CRIME_INT_SOFT1 0x20000000 @@ -117,10 +115,10 @@ #define CRIME_INT_VID_IN2 0x00000002 #define CRIME_INT_VID_IN1 0x00000001 -/* Masks, hard interrupts, soft interrupts. Don't know what to do with these */ -#define CRIME_INTMASK (CRIME_BASE+0x018) -#define CRIME_SOFTINT (CRIME_BASE+0x020) -#define CRIME_HARDINT (CRIME_BASE+0x028) +/* Masks, hard interrupts, soft interrupts. */ +#define CRIME_INTMASK 0x18 +#define CRIME_SOFTINT 0x20 +#define CRIME_HARDINT 0x28 /* * Offset 0x030 -- watchdog register. 33 bits are valid @@ -129,28 +127,28 @@ * Write zero here to reset watchdog */ -#define CRIME_DOG (CRIME_BASE+0x030) +#define CRIME_DOG 0x30 #define CRIME_WATCHDOG CRIME_DOG -#define CRIME_TIME (CRIME_BASE+0x038) -#define CRIME_TIME_MASK 0x0000ffffffffffff -#define CRIME_CPU_ERROR_ADDR (CRIME_BASE+0x040) -#define CRIME_CPU_ERROR_STAT (CRIME_BASE+0x048) -#define CRIME_CPU_ERROR_ENA (CRIME_BASE+0x050) -#define CRIME_VICE_ERROR_ADDR (CRIME_BASE+0x058) -#define CRIME_MEM_CONTROL (CRIME_BASE+0x200) -#define CRIME_MEM_BANK_CTRL0 (CRIME_BASE+0x208) -#define CRIME_MEM_BANK_CTRL1 (CRIME_BASE+0x218) -#define CRIME_MEM_BANK_CTRL2 (CRIME_BASE+0x210) -#define CRIME_MEM_BANK_CTRL3 (CRIME_BASE+0x228) -#define CRIME_MEM_BANK_CTRL4 (CRIME_BASE+0x220) -#define CRIME_MEM_BANK_CTRL5 (CRIME_BASE+0x238) -#define CRIME_MEM_BANK_CTRL6 (CRIME_BASE+0x230) -#define CRIME_MEM_BANK_CTRL7 (CRIME_BASE+0x248) -#define CRIME_MEM_REFRESH_CNTR (CRIME_BASE+0x248) -#define CRIME_MEM_ERROR_STAT (CRIME_BASE+0x250) -#define CRIME_MEM_ERROR_ADDR (CRIME_BASE+0x258) -#define CRIME_MEM_ERROR_ECC_SYN (CRIME_BASE+0x260) -#define CRIME_MEM_ERROR_ECC_CHK (CRIME_BASE+0x268) -#define CRIME_MEM_ERROR_ECC_REPL (CRIME_BASE+0x270) +#define CRIME_TIME 0x38 +#define CRIME_TIME_MASK 0x0000ffffffffffffULL +#define CRIME_CPU_ERROR_ADDR 0x40 +#define CRIME_CPU_ERROR_STAT 0x48 +#define CRIME_CPU_ERROR_ENA 0x50 +#define CRIME_VICE_ERROR_ADDR 0x58 +#define CRIME_MEM_CONTROL 0x0200 +#define CRIME_MEM_BANK_CTRL0 0x0208 +#define CRIME_MEM_BANK_CTRL1 0x0218 +#define CRIME_MEM_BANK_CTRL2 0x0210 +#define CRIME_MEM_BANK_CTRL3 0x0228 +#define CRIME_MEM_BANK_CTRL4 0x0220 +#define CRIME_MEM_BANK_CTRL5 0x0238 +#define CRIME_MEM_BANK_CTRL6 0x0230 +#define CRIME_MEM_BANK_CTRL7 0x0248 +#define CRIME_MEM_REFRESH_CNTR 0x0248 +#define CRIME_MEM_ERROR_STAT 0x0250 +#define CRIME_MEM_ERROR_ADDR 0x0258 +#define CRIME_MEM_ERROR_ECC_SYN 0x0260 +#define CRIME_MEM_ERROR_ECC_CHK 0x0268 +#define CRIME_MEM_ERROR_ECC_REPL 0x0270 #define McGriff CRIME_DOG /* Baseball compatibility */ diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/crimevar.h ./dev/crimevar.h --- /cvs/netbsd/src/sys/arch/sgimips/dev/crimevar.h 1970-01-01 09:00:00.000000000 +0900 +++ ./dev/crimevar.h 2003-09-28 22:21:22.000000000 +0900 @@ -0,0 +1,48 @@ +/* $NetBSD$ */ + +/* + * Copyright (c) 2003 Christopher SEKIYA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed for the + * NetBSD Project. See http://www.netbsd.org/ for + * information about NetBSD. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +struct crime_softc { + struct device sc_dev; + + bus_space_tag_t iot; + bus_space_handle_t ioh; +}; + +extern struct crime_softc *crime_sc; + +void *crime_intr_establish(int, int, int, int (*)(void *), void *); +void crime_intr(u_int); +void crime_intr_mask(unsigned int); diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/if_mecreg.h ./dev/if_mecreg.h --- /cvs/netbsd/src/sys/arch/sgimips/dev/if_mecreg.h 2003-01-04 00:05:29.000000000 +0900 +++ ./dev/if_mecreg.h 2003-09-28 20:38:59.000000000 +0900 @@ -58,18 +58,55 @@ #define MEC_MAC_REVISION 0x00000000e0000000 #define MEC_MAC_REVISION_SHIFT 29 -#define MEC_INT_STATUS 1 << 3 -#define MEC_DMA_CONTROL 2 << 3 -#define MEC_TIMER 3 << 3 -#define MEC_TX_ALIAS 4 << 3 -#define MEC_RX_ALIAS 5 << 3 - -/* 64-32 register, 31-16 write, 15-0 read */ -#define MEC_RING_PTR 6 << 3 - -#define MEC_RX_FIFO 8 << 3 -#define MEC_TX_VECTOR1 11 << 3 -#define MEC_TX_VECTOR2 11 << 3 +#define MEC_INT_STATUS 0x08 +#define MEC_INT_TX_EMPTY 0x00000001 +#define MEC_INT_TX_PACKET_SENT 0x00000002 +#define MEC_INT_TX_LINK_FAIL 0x00000004 +#define MEC_INT_TX_MEM_ERROR 0x00000008 +#define MEC_INT_TX_ABORT 0x00000010 +#define MEC_INT_RX_THRESHOLD 0x00000020 +#define MEC_INT_RX_FIFO_UNDERFLOW 0x00000040 +#define MEC_INT_RX_DMA_UNDERFLOW 0x00000080 +#define MEC_INT_RX_MCL_FIFO_ALIAS 0x00001f00 +#define MEC_INT_TX_RING_BUFFER_ALIAS 0x01ff0000 +#define MEC_INT_RX_SEQUENCE_NUMBER 0x3e000000 +#define MEC_INT_MCAST_HASH_OUTPUT 0x40000000 + +#define MEC_DMA_CONTROL 0x10 +#define MEC_DMA_TX_INT_ENABLE 0x00000001 +#define MEC_DMA_TX_DMA_ENABLE 0x00000002 +#define MEC_DMA_TX_RING_SIZE_MASK 0x0000000c +#define MEC_DMA_RX_INT_THRESHOLD 0x000001f0 +#define MEC_DMA_RX_INT_ENABLE 0x00000200 +#define MEC_DMA_RX_RUNT 0x00000400 +#define MEC_DMA_RX_PACKET_GATHER 0x00000800 +#define MEC_DMA_RX_DMA_OFFSET 0x00007000 +#define MEC_DMA_RX_DMA_ENABLE 0x00008000 + +#define MEC_TIMER 0x18 +#define MEC_TX_ALIAS 0x20 +#define MEC_TX_ALIAS_INT_ENABLE 0x01 + +#define MEC_RX_ALIAS 0x28 +#define MEC_RX_ALIAS_INT_ENABLE 0x200 +#define MEC_RX_ALIAS_INT_THRESHOLD 0x1f0 + +#define MEC_TX_RING_PTR 0x30 +#define MEC_TX_RING_WRITE_PTR 0x000001ff +#define MEC_TX_RING_READ_PTR 0x01ff0000 +#define MEC_TX_RING_PTR_ALIAS 0x38 + +#define MEC_RX_FIFO 0x40 +#define MEC_RX_FIFO_ELEMENT_COUNT 0x0000001f +#define MEC_RX_FIFO_READ_PTR 0x00000f00 +#define MEC_RX_FIFO_GEN_NUMBER 0x00001000 +#define MEC_RX_FIFO_WRITE_PTR 0x000f0000 +#define MEC_RX_FIFO_GEN_NUMBER_2 0x00100000 + +#define MEC_RX_FIFO_ALIAS1 0x48 +#define MEC_RX_FIFO_ALIAS2 0x50 +#define MEC_TX_VECTOR 0x58 +#define MEC_IRQ_VECTOR 0x58 #define MEC_PHY_DATA 12 << 3 #define MEC_PHY_DATA_BUSY 0x8000 @@ -84,26 +121,56 @@ #define MEC_PHY_BACKOFF 15 << 3 -#define MEC_MSGQUEUE 16 << 3 - #define MEC_STATION 0xa0 #define MEC_STATION_ALT 0xa8 #define MEC_STATION_MASK 0x0000ffffffffffff - -/* DMA control values */ -#define MEC_DMA_TX_INT_EN 0x0001 -#define MEC_DMA_TX_DMA_EN 0x0002 -#define MEC_DMA_TX_RINGMSK 0x000c -#define MEC_DMA_TX_8K 0x0000 -#define MEC_DMA_TX_16K 0x0004 -#define MEC_DMA_TX_32K 0x0008 -#define MEC_DMA_TX_64K 0x000c -#define MEC_DMA_TX_RINGMSK_SHIFT 2 -#define MEC_DMA_RX_THRSHD 0x01f0 -#define MEC_DMA_RX_INT_EN 0x0200 -#define MEC_DMA_RX_RUNTS_EN 0x0400 -#define MEC_DMA_RX_GATHER_EN 0x0800 -#define MEC_DMA_RX_OFFSET 0x7000 -#define MEC_DMA_RX_OFFSET_SHIFT 12 -#define MEC_DMA_RX_DMA_EN 0x8000 +#define MEC_MULTICAST 0xb0 +#define MEC_TX_RING_BASE 0xb8 +#define MEC_TX_PKT1_CMD_1 0xc0 +#define MEC_TX_PKT1_BUFFER_1 0xc8 +#define MEC_TX_PKT1_BUFFER_2 0xd0 +#define MEC_TX_PKT1_BUFFER_3 0xd8 +#define MEC_TX_PKT2_CMD_1 0xe0 +#define MEC_TX_PKT2_BUFFER_1 0xe8 +#define MEC_TX_PKT2_BUFFER_2 0xf0 +#define MEC_TX_PKT2_BUFFER_3 0xf8 +#define MEC_MCL_RX_FIFO 0x100 + +/* these structs should be moved to if_mecvar.h */ + +/* the first eight bytes of the tx vector are status. it can be a command + header, a transmit concatenation pointer, or a status vector. */ + +#define MEC_TX_COMMAND_HDR_LENGTH 0x0000ffff /* length, bytes-1 */ +#define MEC_TX_COMMAND_HDR_START_OFFSET 0x007f0000 /* minimum 8 bytes */ +#define MEC_TX_COMMAND_HDR_TX_IRQ 0x00800000 /* raise TX DMA on abort */ +#define MEC_TX_COMMAND_CONCAT_1 0x01000000 +#define MEC_TX_COMMAND_CONCAT_2 0x02000000 +#define MEC_TX_COMMAND_CONCAT_3 0x04000000 + +#define MEC_TX_CONCAT_PTR_ADDRESS 0x00000000fffffff8 +#define MEC_TX_CONCAT_PTR_LENGTH 0x0000ffff00000000 + +#define MEC_TX_STATUS_VECTOR_LENGTH 0x000000000000ffff +#define MEC_TX_STATUS_VECTOR_COL_RETRY 0x00000000000f0000 +#define MEC_TX_STATUS_VECTOR_LATE_COLLISION 0x0000000000100000 +#define MEC_TX_STATUS_VECTOR_CRC_ERROR 0x0000000000200000 +#define MEC_TX_STATUS_VECTOR_DEFERRED 0x0000000000400000 +#define MEC_TX_STATUS_VECTOR_TX_SUCCESS 0x0000000000800000 +#define MEC_TX_STATUS_VECTOR_TOOBIG 0x0000000001000000 +#define MEC_TX_STATUS_VECTOR_UNDERRUN 0x0000000002000000 +#define MEC_TX_STATUS_VECTOR_COLLISIONS 0x0000000004000000 +#define MEC_TX_STATUS_VECTOR_EX_DEFERRAL 0x0000000008000000 +#define MEC_TX_STATUS_VECTOR_COLLIDED 0x0000000010000000 +#define MEC_TX_STATUS_VECTOR_VALID 0x8000000000000000 + +struct tx_fifo { + u_int64_t control; + u_int8_t data[120]; +}; + +struct rx_fifo { + u_int64_t control; + u_int8_t data[120]; +}; diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/imc.c ./dev/imc.c --- /cvs/netbsd/src/sys/arch/sgimips/dev/imc.c 2003-08-01 01:51:53.000000000 +0900 +++ ./dev/imc.c 2003-09-28 21:07:10.000000000 +0900 @@ -81,7 +81,7 @@ /* * The IMC is an INDY/INDIGO2 thing. */ - if (mach_type != MACH_SGI_IP22) + if ((mach_type != MACH_SGI_IP22) && (mach_type != MACH_SGI_IP28)) return (0); /* Make sure it's actually there and readable */ diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/lpt_mace.c ./dev/lpt_mace.c --- /cvs/netbsd/src/sys/arch/sgimips/dev/lpt_mace.c 2003-08-01 01:51:53.000000000 +0900 +++ ./dev/lpt_mace.c 2003-09-28 21:08:28.000000000 +0900 @@ -1,6 +1,7 @@ /* $NetBSD: lpt_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $ */ /* + * Copyright (c) 2003 Christopher SEKIYA * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -53,6 +54,7 @@ #include #include #include +#include #include @@ -77,7 +79,11 @@ struct cfdata *match; void *aux; { - return 1; + + if (mach_type == MACH_SGI_IP32) + return (1); + + return (0); } static void @@ -86,13 +92,23 @@ struct device *self; void *aux; { -#if 0 struct lpt_mace_softc *msc = (void *)self; struct lpt_softc *sc = &msc->sc_lpt; struct mace_attach_args *maa = aux; -#endif - printf(": stub\n"); + sc->sc_iot = maa->maa_st; + + if (bus_space_subregion(sc->sc_iot, maa->maa_sh, + maa->maa_offset, LPT_NPORTS, &sc->sc_ioh) != 0) { + printf(": can't map i/o space\n"); + return; + } + + printf("\n"); + + lpt_attach_subr(sc); + + mace_intr_establish(maa->maa_intr, maa->maa_intrmask, lptintr, sc); return; } diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/macaureg.h ./dev/macaureg.h --- /cvs/netbsd/src/sys/arch/sgimips/dev/macaureg.h 2002-03-17 03:51:27.000000000 +0900 +++ ./dev/macaureg.h 2003-09-28 20:38:59.000000000 +0900 @@ -33,11 +33,23 @@ /* * MACE audio CODEC register definitions * - * With an Analog Device AD1843 CODEC (?) + * AD1843 CODEC behind simple DMA glue. */ -#define MACAU_CONTROL_STATUS 0x00 -#define MACAU_CODEC_STATUS_CNTL 0x08 +#define MACAU_CONTROL 0x00 +#define MACAU_CONTROL_RESET 0x00000001 +#define MACAU_CONTROL_CODEC_PRESENT 0x00000002 +#define MACAU_CONTROL_RP1_ALIAS_MASK 0x000001fc +#define MACAU_CONTROL_RP2_ALIAS_MASK 0x0000fe00 +#define MACAU_CONTROL_RP3_ALIAS_MASK 0x007f0000 +#define MACAU_CONTROL_VOLUME_1 0x00800000 +#define MACAU_CONTROL_VOLUME_2 0x01000000 + +#define MACAU_CODEC_CONTROL 0x08 +#define MACAU_CODEC_CONTROL_SHIFT 17 +#define MACAU_CODEC_CONTROL_READ 0x00010000 +#define MACAU_CODEC_CONTROL_DATA_MASK 0x0000ffff + #define MACAU_CODEC_STATUS_INPUT_MASK 0x10 #define MACAU_CODEC_STATUS_INPUT 0x18 #define MACAU_CH1_IN_RING_CONTROL 0x20 @@ -52,3 +64,39 @@ #define MACAU_CH3_OUT_READ_POINTER 0x68 #define MACAU_CH3_OUT_WRITE_POINTER 0x70 #define MACAU_CH3_OUT_RING_DEPTH 0x78 + +/* The ad1843 isn't register-compatible with the ad1848 */ + +#define AD1843_STATUS_REVISION 0x00 +#define AD1843_CHANNEL_STATUS 0x01 +#define AD1843_ADC_SOURCE 0x02 +#define AD1843_DAC2_MIXER 0x03 +#define AD1843_AUX1_MIXER 0x04 +#define AD1843_AUX2_MIXER 0x05 +#define AD1843_AUX3_MIX 6 +#define AD1843_MIC_MIX 7 +#define AD1843_MONO_MIX_MISC 8 /* select mono in and misc mixing */ +#define AD1843_DAC1_GATTN 9 /* gain/attenuation for DAC1 */ +#define AD1843_DAC2_GATTN 10 +#define AD1843_DAC1_DIGITAL_ATTEN 11 /* digital only attenuation for DAC1 */ +#define AD1843_DAC2_DIGITAL_ATTEN 12 /* digital only attenuation for DAC2 */ +#define AD1843_ADC_DAC1_MIX 13 /* ADC to DAC1 digital mixing */ +#define AD1843_ADC_DAC2_MIX 14 /* ADC to DAC2 digital mixing */ +#define AD1843_CLK_SRC_SELECT 15 /* select rate clock source */ +#define AD1843_CLK_GEN1_MODE 16 /* cntrl mode: video lck, PLL gain, etc */ +#define AD1843_CLK_GEN1_RATE 17 /* sample rate */ +#define AD1843_CLK_GEN1_PHASE 18 /* phase shift sample clk */ +#define AD1843_CLK_GEN2_MODE 19 /* cntrl mode: video lck, PLL gain, etc */ +#define AD1843_CLK_GEN2_RATE 20 /* sample rate */ +#define AD1843_CLK_GEN2_PHASE 21 /* phase shift sample clk */ +#define AD1843_CLK_GEN3_MODE 22 /* cntrl mode: video lck, PLL gain, etc */ +#define AD1843_CLK_GEN3_RATE 23 /* sample rate */ +#define AD1843_CLK_GEN3_PHASE 24 /* phase shift sample clk */ +#define AD1843_FILTER_MODE 25 /* digital filter mode */ +#define AD1843_SERIAL 26 /* serial interface and sampl format */ +#define AD1843_CH_POWERDOWN 27 /* channel power down */ +#define AD1843_CONFIG 28 /* converter pwr dwn, clk out enables */ +#define AD1843_RESERVED_29 29 +#define AD1843_RESERVED_30 30 +#define AD1843_RESERVED_31 31 + diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/mace.c ./dev/mace.c --- /cvs/netbsd/src/sys/arch/sgimips/dev/mace.c 2003-08-01 01:51:53.000000000 +0900 +++ ./dev/mace.c 2003-09-28 22:19:41.000000000 +0900 @@ -1,6 +1,8 @@ /* $NetBSD: mace.c,v 1.12 2003/07/15 03:35:52 lukem Exp $ */ /* + * Copyright (c) 2003 Christopher Sekiya + * Copyright (c) 2002,2003 Rafal K. Boni * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -34,40 +36,80 @@ /* * O2 MACE + * + * The MACE is weird -- although it is a 32-bit device, writes only seem to + * work properly if they are 64-bit-at-once writes (at least, out in ISA + * space and probably MEC space -- the PCI stuff seems to be okay with _4). + * Therefore, the _8* routines are used even though the top 32 bits are + * thrown away. */ #include __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.12 2003/07/15 03:35:52 lukem Exp $"); #include -#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#define _SGIMIPS_BUS_DMA_PRIVATE +#include #include #include #include -#include #include #include #include +#include #include #include "locators.h" +#define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ + +struct { + unsigned int irq; + unsigned int intrmask; + int (*func)(void *); + void *arg; +} maceintrtab[MACE_NINTR]; + struct mace_softc { struct device sc_dev; + + bus_space_tag_t iot; + bus_space_handle_t ioh; + bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ + int nsegs; + bus_dma_segment_t seg; + bus_dmamap_t map; + + void *isa_ringbuffer; }; static int mace_match(struct device *, struct cfdata *, void *); static void mace_attach(struct device *, struct device *, void *); static int mace_print(void *, const char *); static int mace_search(struct device *, struct cfdata *, void *); -void mace_intr(int irqs); CFATTACH_DECL(mace, sizeof(struct mace_softc), mace_match, mace_attach, NULL, NULL); +#if defined(BLINK) +static struct callout mace_blink_ch = CALLOUT_INITIALIZER; +static void mace_blink(void *); +#endif + static int mace_match(parent, match, aux) struct device *parent; @@ -90,25 +132,90 @@ struct device *self; void *aux; { - u_int32_t id; + struct mace_softc *sc = (struct mace_softc *)self; + struct mainbus_attach_args *ma = aux; + u_int32_t scratch; + + sc->iot = 3; + sc->dmat = &sgimips_default_bus_dma_tag; + + if (bus_space_map(sc->iot, ma->ma_addr, NULL, + BUS_SPACE_MAP_LINEAR, &sc->ioh)) + panic("mace_attach: could not allocate memory\n"); + +#if 0 + /* + * There's something deeply wrong with the alloc() routine -- it + * returns a pointer to memory that is used by the kernel i/o + * buffers. Disable for now. + */ + + if ((bus_dmamem_alloc(sc->dmat, 32768, PAGE_SIZE, 32768, + &sc->seg, 1, &sc->nsegs, BUS_DMA_NOWAIT)) != 0) { + printf(": unable to allocate DMA memory\n"); + return; + } + + if ((bus_dmamem_map(sc->dmat, &sc->seg, sc->nsegs, 32768, + (caddr_t *)&sc->isa_ringbuffer, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) + != 0) { + printf(": unable to map control data\n"); + return; + } + + if ((bus_dmamap_create(sc->dmat, 32768, 1, 32768, 0, + BUS_DMA_NOWAIT, &sc->map)) != 0) { + printf(": unable to create DMA map for control data\n"); + return; + } + + if ((scratch = bus_dmamap_load(sc->dmat, sc->map, sc->isa_ringbuffer, + 32768, NULL, BUS_DMA_NOWAIT)) != 0) { + printf(": unable to load DMA map for control data %i\n", + scratch); + } + + memset(sc->isa_ringbuffer, 0, 32768); + + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_RINGBASE, + MIPS_KSEG1_TO_PHYS(sc->isa_ringbuffer) & 0xffff8000); - id = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_REV_INFO_R); - aprint_normal(": rev %x", id); - printf("\n"); + aprint_normal(" isa ringbuffer 0x%x size 32k", + MIPS_KSEG1_TO_PHYS((unsigned long)sc->isa_ringbuffer)); +#endif + + aprint_normal("\n"); aprint_debug("%s: isa sts %llx\n", self->dv_xname, - *(volatile u_int64_t *)0xbf310010); + bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); aprint_debug("%s: isa msk %llx\n", self->dv_xname, - *(volatile u_int64_t *)0xbf310018); + bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); - /* - * Disable interrupts. These are enabled and unmasked during - * interrupt establishment + /* + * Turn on all ISA interrupts. These are actually masked and + * registered via the CRIME, as the MACE ISA interrupt mask is + * really whacky and nigh on impossible to map to a sane autoconfig + * scheme. */ - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_ADDR) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_CONTROL) = 0xff008500; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK) = 0; + + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffffffff); + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); + + /* set up LED for solid green or blink, if that's your fancy */ + scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); + scratch |= MACE_ISA_LED_RED; + scratch &= ~(MACE_ISA_LED_GREEN); + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); + +#if defined(BLINK) + mace_blink(sc); +#endif + + /* Initialize the maceintr elements to sane values */ + for (scratch = 0; scratch < MACE_NINTR; scratch++) { + maceintrtab[scratch].func = NULL; + maceintrtab[scratch].irq = 0; + } config_search(mace_search, self, NULL); } @@ -126,12 +233,10 @@ if (maa->maa_offset != MACECF_OFFSET_DEFAULT) aprint_normal(" offset 0x%lx", maa->maa_offset); -#if 0 if (maa->maa_intr != MACECF_INTR_DEFAULT) aprint_normal(" intr %d", maa->maa_intr); - if (maa->maa_offset != MACECF_STRIDE_DEFAULT) - aprint_normal(" stride 0x%lx", maa->maa_stride); -#endif + if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) + aprint_normal(" intrmask 0x%x", maa->maa_intrmask); return UNCONF; } @@ -142,18 +247,18 @@ struct cfdata *cf; void *aux; { + struct mace_softc *sc = (struct mace_softc *)parent; struct mace_attach_args maa; int tryagain; do { maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; -#if 0 maa.maa_intr = cf->cf_loc[MACECF_INTR]; - maa.maa_stride = cf->cf_loc[MACECF_STRIDE]; -#endif - maa.maa_st = 3; - /* XXX */ - maa.maa_sh = MIPS_PHYS_TO_KSEG1(maa.maa_offset + 0x1f000000); + maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; + maa.maa_st = SGIMIPS_BUS_SPACE_MACE; + maa.maa_sh = sc->ioh; + maa.maa_dmat = &sgimips_default_bus_dma_tag; + maa.isa_ringbuffer = sc->isa_ringbuffer; tryagain = 0; if (config_match(parent, cf, &maa) > 0) { @@ -166,13 +271,6 @@ return 0; } -#define MACE_NINTR 8 /* XXX */ - -struct { - int (*func)(void *); - void *arg; -} maceintrtab[MACE_NINTR]; - void * mace_intr_establish(intr, level, func, arg) int intr; @@ -180,38 +278,81 @@ int (*func)(void *); void *arg; { - u_int64_t mask; + int i; if (intr < 0 || intr >= 8) panic("invalid interrupt number"); - if (maceintrtab[intr].func != NULL) - return NULL; /* panic("Cannot share MACE interrupts!"); */ + for (i = 0; i < MACE_NINTR; i++) + if (maceintrtab[intr].func == NULL) { + maceintrtab[intr].func = func; + maceintrtab[intr].arg = arg; + maceintrtab[intr].irq = (1 << intr); + maceintrtab[intr].intrmask = level; + break; + } - maceintrtab[intr].func = func; - maceintrtab[intr].arg = arg; - mask = *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK); - mask |= (1 << intr); - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK) = mask; - aprint_debug("mace: established interrupt %d (level %i)\n", intr, level); - aprint_debug("mace: CRM_MASK now %llx\n", *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK)); + crime_intr_mask(intr); + aprint_normal("mace: established interrupt %d (level %x)\n", + intr, level); return (void *)&maceintrtab[intr]; } void mace_intr(int irqs) { + u_int64_t isa_irq, isa_mask; int i; - /* printf("mace_intr: irqs %x\n", irqs); */ + /* irq 4 is the ISA cascade interrupt. Must handle with care. */ + if ( irqs & (1 << 4)) { + isa_mask = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(0x1f000000 + + MACE_ISA_INT_MASK)); + isa_irq = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(0x1f000000 + + MACE_ISA_INT_STATUS)); + for (i = 0; i < MACE_NINTR; i++) { + if ((maceintrtab[i].irq == (1 << 4)) && + (isa_irq & maceintrtab[i].intrmask)) { + if (isa_irq & 0xfc000000) + printf("dispatching\n"); - for (i = 0; i < MACE_NINTR; i++) { - if (irqs & (1 << i)) { - if (maceintrtab[i].func != NULL) (maceintrtab[i].func)(maceintrtab[i].arg); - else - printf("Unexpected mace interrupt %d\n", i); - } + } + } +#if 0 + mips3_sd((u_int64_t *)MIPS_PHYS_TO_KSEG1(0x1f000000 + + MACE_ISA_INT_STATUS), isa_mask); +#endif + irqs &= ~(1 << 4); } + + for (i = 0; i < MACE_NINTR; i++) + if ((irqs & maceintrtab[i].irq)) + (maceintrtab[i].func)(maceintrtab[i].arg); } +#if defined(BLINK) +static void +mace_blink(void *self) +{ + struct mace_softc *sc = (struct mace_softc *) self; + register int s; + int value; + + s = splhigh(); + value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); + value ^= MACE_ISA_LED_GREEN; + bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); + splx(s); + /* + * Blink rate is: + * full cycle every second if completely idle (loadav = 0) + * full cycle every 2 seconds if loadav = 1 + * full cycle every 3 seconds if loadav = 2 + * etc. + */ + s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); + callout_reset(&mace_blink_ch, s, mace_blink, sc); + +} +#endif diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/macereg.h ./dev/macereg.h --- /cvs/netbsd/src/sys/arch/sgimips/dev/macereg.h 2003-01-04 00:05:29.000000000 +0900 +++ ./dev/macereg.h 2003-09-28 20:38:59.000000000 +0900 @@ -32,14 +32,13 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#define MACE_BASE 0x1f000000 -#define MACE_PCI (MACE_BASE + 0x080000) -#define MACE_PCI_ERROR_ADDR (MACE_PCI+0x0) -#define MACE_PCI_ERROR_FLAGS (MACE_PCI+0x4) +/* PCI definitions (offset 0x080000) */ -#define MACE_PCI_CONTROL (MACE_PCI+0x8) -#define MACE_PCI_CONTROL_INT(x) BIT(x) +#define MACE_PCI_ERROR_ADDR 0x00 +#define MACE_PCI_ERROR_FLAGS 0x04 + +#define MACE_PCI_CONTROL 0x08 #define MACE_PCI_CONTROL_INT_MASK 0xff #define MACE_PCI_CONTROL_SERR_ENA 0x0100 #define MACE_PCI_CONTROL_ARB_N6 0x0200 @@ -50,23 +49,21 @@ #define MACE_PCI_CONTROL_ARB_N5 0x4000 #define MACE_PCI_CONTROL_PARK_LIU 0x8000 -/* #define MACE_PCI_CONTROL_INV_INT(x) BIT(16+x) #define MACE_PCI_CONTROL_INV_INT_MASK 0x00ff0000 -#define MACE_PCI_CONTROL_OVERRUN_INT BIT(24) -#define MACE_PCI_CONTROL_PARITY_INT BIT(25) -#define MACE_PCI_CONTROL_SERR_INT BIT(26) -#define MACE_PCI_CONTROL_IT_INT BIT(27) -#define MACE_PCI_CONTROL_RE_INT BIT(28) -#define MACE_PCI_CONTROL_DPED_INT BIT(29) -#define MACE_PCI_CONTROL_TAR_INT BIT(30) -#define MACE_PCI_CONTROL_MAR_INT BIT(31) -*/ +#define MACE_PCI_CONTROL_OVERRUN_INT 0x01000000 +#define MACE_PCI_CONTROL_PARITY_INT 0x02000000 +#define MACE_PCI_CONTROL_SERR_INT 0x04000000 +#define MACE_PCI_CONTROL_IT_INT 0x08000000 +#define MACE_PCI_CONTROL_RE_INT 0x10000000 +#define MACE_PCI_CONTROL_DPED_INT 0x20000000 +#define MACE_PCI_CONTROL_TAR_INT 0x40000000 +#define MACE_PCI_CONTROL_MAR_INT 0x80000000 -#define MACE_PCI_REV_INFO_R (MACE_PCI+0xC) -#define MACE_PCI_FLUSH_W (MACE_PCI+0xC) -#define MACE_PCI_CONFIG_ADDR (MACE_PCI+0xCF4) -#define MACE_PCI_CONFIG_DATA (MACE_PCI+0xCF8) +#define MACE_PCI_REV_INFO_R 0x0c +#define MACE_PCI_FLUSH_W 0x0c +#define MACE_PCI_CONFIG_ADDR 0xcf8 +#define MACE_PCI_CONFIG_DATA 0xcfc #define MACE_PCI_LOW_MEMORY 0x1A000000 #define MACE_PCI_LOW_IO 0x18000000 #define MACE_PCI_NATIVE_VIEW 0x40000000 @@ -74,20 +71,16 @@ #define MACE_PCI_HI_MEMORY 0x280000000 #define MACE_PCI_HI_IO 0x100000000 +#define MACE_VIN1 0x100000 +#define MACE_VIN2 0x180000 +#define MACE_VOUT 0x200000 +#define MACE_PERIF 0x300000 +#define MACE_ISA_EXT 0x380000 - -#define MACE_VIN1 (MACE_BASE + 0x100000) -#define MACE_VIN2 (MACE_BASE + 0x180000) -#define MACE_VOUT (MACE_BASE + 0x200000) -#define MACE_ENET (MACE_BASE + 0x280000) -#define MACE_PERIF (MACE_BASE + 0x300000) -#define MACE_ISA_EXT (MACE_BASE + 0x380000) - -#define MACE_AUDIO (MACE_PERIF + 0x00000) #define MACE_ISA (MACE_PERIF + 0x10000) #define MACE_KBDMS (MACE_PERIF + 0x20000) #define MACE_I2C (MACE_PERIF + 0x30000) -#define MACE_UST_MSC (MACE_PERIF + 0X40000) +#define MACE_UST_MSC (MACE_PERIF + 0x40000) @@ -144,8 +137,8 @@ /* Interrupt Status and Mask Registers (32 bits) */ -#define MACE_ISA_INT_STATUS (MACE_ISA+0x0010) -#define MACE_ISA_INT_MASK (MACE_ISA+0x0018) +#define MACE_ISA_INT_STATUS (0x310010) +#define MACE_ISA_INT_MASK (0x310018) /* bit definitions */ #define MACE_ISA_INT_RTC_IRQ (0x00000100) diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/macevar.h ./dev/macevar.h --- /cvs/netbsd/src/sys/arch/sgimips/dev/macevar.h 2003-01-04 00:05:29.000000000 +0900 +++ ./dev/macevar.h 2003-09-28 21:21:26.000000000 +0900 @@ -35,14 +35,13 @@ struct mace_attach_args { bus_space_tag_t maa_st; bus_space_handle_t maa_sh; + bus_dma_tag_t maa_dmat; + void *isa_ringbuffer; -/* ? */ long maa_offset; int maa_intr; -#if 0 - int maa_stride; -#endif + int maa_intrmask; }; -extern void * mace_intr_establish(int, int, int (*)(void *), void *); -extern void mace_intr(int); +void * mace_intr_establish(int, int, int (*)(void *), void *); +void mace_intr(int); diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/mcclock_mace.c ./dev/mcclock_mace.c --- /cvs/netbsd/src/sys/arch/sgimips/dev/mcclock_mace.c 2003-08-01 01:51:53.000000000 +0900 +++ ./dev/mcclock_mace.c 2003-09-28 21:22:15.000000000 +0900 @@ -113,6 +113,7 @@ static int mcclock_mace_match(struct device *parent, struct cfdata *match, void *aux) { + return 1; } @@ -123,7 +124,9 @@ struct mace_attach_args *maa = aux; sc->sc_st = maa->maa_st; - sc->sc_sh = maa->maa_sh; + if (bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset, NULL, &sc->sc_sh) ) + panic("mcclock_mace_attach: couldn't map"); /* * We want a fixed format: 24-hour, BCD data, so just force the diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/dev/pckbc_mace.c ./dev/pckbc_mace.c --- /cvs/netbsd/src/sys/arch/sgimips/dev/pckbc_mace.c 2003-08-01 01:51:53.000000000 +0900 +++ ./dev/pckbc_mace.c 2003-09-28 21:24:46.000000000 +0900 @@ -1,6 +1,7 @@ /* $NetBSD: pckbc_mace.c,v 1.6 2003/07/15 03:35:52 lukem Exp $ */ /* + * Copyright (c) 2003 Christopher SEKIYA * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -37,22 +38,17 @@ #include #include -#include -#include -#include -#include -#include -#include -#include #include -#include -#include +#include #include +#include +#include +#include +#include -#include -#include #include #include +#include #include @@ -62,11 +58,12 @@ struct pckbc_mace_softc { struct pckbc_softc sc_pckbc; - /* XXX intr cookie */ + int sc_irq[PCKBC_NSLOTS]; }; static int pckbc_mace_match(struct device *, struct cfdata *, void *); static void pckbc_mace_attach(struct device *, struct device *, void *); +void pckbc_mace_intr_establish(struct pckbc_softc *, pckbc_slot_t); CFATTACH_DECL(pckbc_mace, sizeof(struct pckbc_mace_softc), pckbc_mace_match, pckbc_mace_attach, NULL, NULL); @@ -77,7 +74,10 @@ struct cfdata *match; void *aux; { - return 1; + if (mach_type == MACH_SGI_IP32) + return (1); + + return (0); } static void @@ -86,15 +86,38 @@ struct device *self; void *aux; { -#if 0 struct pckbc_mace_softc *msc = (void *)self; struct pckbc_softc *sc = &msc->sc_pckbc; struct mace_attach_args *maa = aux; -#endif + struct pckbc_internal *t; + bus_space_handle_t ioh_d, ioh_c; + + msc->sc_irq[PCKBC_KBD_SLOT] = + msc->sc_irq[PCKBC_AUX_SLOT] = maa->maa_intr; + + sc->intr_establish = pckbc_mace_intr_establish; + + if (bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset, 1, &ioh_d) || + bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset + 0x20, 1, &ioh_c)) + panic("pckbc_attach: couldn't map"); + + t = malloc(sizeof(struct pckbc_internal), M_DEVBUF, M_WAITOK|M_ZERO); + t->t_iot = maa->maa_st; + t->t_ioh_d = ioh_d; + t->t_ioh_c = ioh_c; + t->t_addr = maa->maa_sh; + t->t_cmdbyte = KC8_CPU; /* Enable ports */ + callout_init(&t->t_cleanup); - printf(": stub\n"); + t->t_sc = sc; + sc->id = t; - return; + printf("\n"); + + /* Finish off the attach. */ + pckbc_attach(sc); } /* XXX */ @@ -108,5 +131,15 @@ pckbc_tag_t kbctag; pckbc_slot_t kbcslot; { + return (ENXIO); } + +void +pckbc_mace_intr_establish(sc, slot) + struct pckbc_softc *sc; + pckbc_slot_t slot; +{ + + mace_intr_establish(5, 0, pckbcintr, sc); +} diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/hpc/hpc.c ./hpc/hpc.c --- /cvs/netbsd/src/sys/arch/sgimips/hpc/hpc.c 2003-09-28 16:41:13.000000000 +0900 +++ ./hpc/hpc.c 2003-09-28 20:38:59.000000000 +0900 @@ -151,6 +151,7 @@ switch (mach_type) { case MACH_SGI_IP22: + case MACH_SGI_IP28: hpctype = 3; if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) sysmask = HPCDEV_IP22; diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/include/bus.h ./include/bus.h --- /cvs/netbsd/src/sys/arch/sgimips/include/bus.h 2003-07-14 00:00:41.000000000 +0900 +++ ./include/bus.h 2003-09-28 21:04:16.000000000 +0900 @@ -61,6 +61,15 @@ typedef u_long bus_space_handle_t; /* + * Values for sgimips bus space tag, not to be used directly by MI code. + */ +#define SGIMIPS_BUS_SPACE_NORMAL 0 +#define SGIMIPS_BUS_SPACE_HPC 1 +#define SGIMIPS_BUS_SPACE_MEM 2 +#define SGIMIPS_BUS_SPACE_MACE 3 +#define SGIMIPS_BUS_SPACE_IO 4 + +/* * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, * bus_size_t size, int flags, bus_space_handle_t *bshp); * @@ -138,10 +147,7 @@ (wbflush(), /* XXX */ \ (void) t, (*(volatile u_int32_t *)((h) + (o)))) -/* XXX Make sure to use 64-bit loads. */ -#define bus_space_read_8(t, h, o) \ -(wbflush(), /* XXX */ \ - (void) t, (*(volatile u_int64_t *)((h) + (o)))) +#define bus_space_read_8(t, h, o) mips3_ld((u_int64_t *)((h) + (o))) /* * void bus_space_read_multi_N(bus_space_tag_t tag, @@ -241,13 +247,7 @@ wbflush(); /* XXX */ \ } while (0) -/* XXX Make sure to use 64-bit stores. */ -#define bus_space_write_8(t, h, o, v) \ -do { \ - (void) t; \ - *(volatile u_int64_t *)((h) + (o)) = (v); \ - wbflush(); /* XXX */ \ -} while (0) +#define bus_space_write_8(t, h, o, v) (mips3_sd((u_int64_t *)((h) + (o)), (v))) /* * void bus_space_write_multi_N(bus_space_tag_t tag, diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/include/pci_machdep.h ./include/pci_machdep.h --- /cvs/netbsd/src/sys/arch/sgimips/include/pci_machdep.h 2002-06-08 17:14:57.000000000 +0900 +++ ./include/pci_machdep.h 2003-09-28 20:38:59.000000000 +0900 @@ -55,7 +55,8 @@ pcireg_t (*pc_conf_read)(pci_chipset_tag_t, pcitag_t, int); void (*pc_conf_write)(pci_chipset_tag_t, pcitag_t, int, pcireg_t); -/* XXX */ + bus_space_tag_t iot; + bus_space_handle_t ioh; }; extern struct sgimips_bus_dma_tag pci_bus_dma_tag; diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/pci/macepci.c ./pci/macepci.c --- /cvs/netbsd/src/sys/arch/sgimips/pci/macepci.c 2003-08-01 01:51:55.000000000 +0900 +++ ./pci/macepci.c 2003-09-28 21:40:38.000000000 +0900 @@ -1,7 +1,7 @@ /* $NetBSD: macepci.c,v 1.12 2003/07/15 03:35:54 lukem Exp $ */ /* - * Copyright (c) 2001 Christopher Sekiya + * Copyright (c) 2001,2003 Christopher Sekiya * Copyright (c) 2000 Soren S. Jorvang * All rights reserved. * @@ -45,6 +45,7 @@ #include #include #include +#include #include #include @@ -92,11 +93,11 @@ int pciaddr_do_resource_allocate(pci_chipset_tag_t pc, pcitag_t tag, int mapreg, void *ctx, int type, bus_addr_t *addr, bus_size_t size); -unsigned int ioaddr_base = 0x3000; +unsigned int ioaddr_base = 0x1000; unsigned int memaddr_base = 0x80100000; CFATTACH_DECL(macepci, sizeof(struct macepci_softc), - macepci_match, macepci_attach, NULL, NULL); + macepci_match, macepci_attach, NULL, NULL); static int macepci_match(parent, match, aux) @@ -104,7 +105,11 @@ struct cfdata *match; void *aux; { - return 1; + + if (mach_type == MACH_SGI_IP32) + return (1); + + return (0); } static void @@ -121,25 +126,42 @@ pcitag_t devtag; int device, rev; - rev = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_REVISION); + if (bus_space_subregion(maa->maa_st, maa->maa_sh, + maa->maa_offset, NULL, &pc->ioh) ) + panic("macepci_attach: couldn't map"); + + pc->iot = maa->maa_st; + + rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION); printf(": rev %d\n", rev); pc->pc_conf_read = macepci_conf_read; pc->pc_conf_write = macepci_conf_write; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_ADDR) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_CONTROL) = 0xff008500; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_HARDINT) = 0; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_SOFTINT) = 0; + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0); + + /* Turn on PCI error interrupts */ + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL, + MACE_PCI_CONTROL_SERR_ENA | + MACE_PCI_CONTROL_PARITY_ERR | + MACE_PCI_CONTROL_PARK_LIU | + MACE_PCI_CONTROL_OVERRUN_INT | + MACE_PCI_CONTROL_PARITY_INT | + MACE_PCI_CONTROL_SERR_INT | + MACE_PCI_CONTROL_IT_INT | + MACE_PCI_CONTROL_RE_INT | + MACE_PCI_CONTROL_DPED_INT | + MACE_PCI_CONTROL_TAR_INT | + MACE_PCI_CONTROL_MAR_INT); - /* Only fix up the PCI slot, leave SCSI 0 & 1 as is */ - for (device = 3; device < 4; device++) { + /* Must fix up all PCI devices, ahc_pci expects proper i/o mapping */ + for (device = 1; device < 4; device++) { const struct pci_quirkdata *qd; int function, nfuncs; pcireg_t bhlcr, id; - devtag = pci_make_tag(0, 0, device, 0); + devtag = pci_make_tag(pc, 0, device, 0); id = pci_conf_read(pc, devtag, PCI_ID_REG); /* Invalid vendor ID value? */ @@ -160,7 +182,7 @@ nfuncs = 1; for (function = 0; function < nfuncs; function++) { - devtag = pci_make_tag(0, 0, device, function); + devtag = pci_make_tag(pc, 0, device, function); id = pci_conf_read(pc, devtag, PCI_ID_REG); /* Invalid vendor ID value? */ @@ -170,7 +192,7 @@ if (PCI_VENDOR(id) == 0) continue; - pciaddr_resource_manage(0, devtag, NULL, NULL); + pciaddr_resource_manage(pc, devtag, NULL, NULL); } } @@ -178,15 +200,15 @@ * Enable all MACE PCI interrupts. They will be masked by * the CRIME code. */ - control = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL); + control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL); control |= CONTROL_INT_MASK; - bus_space_write_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL, control); + bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control); #if NPCI > 0 memset(&pba, 0, sizeof pba); pba.pba_busname = "pci"; -/*XXX*/ pba.pba_iot = 4; -/*XXX*/ pba.pba_memt = 2; +/*XXX*/ pba.pba_iot = SGIMIPS_BUS_SPACE_IO; +/*XXX*/ pba.pba_memt = SGIMIPS_BUS_SPACE_MEM; pba.pba_dmat = &pci_bus_dma_tag; pba.pba_dmat64 = NULL; pba.pba_bus = 0; @@ -200,8 +222,7 @@ pba.pba_flags &= ~PCI_FLAGS_IO_ENABLED; /* Buggy? */ #endif - mace_intr_establish(7, IPL_NONE, macepci_intr, sc); - /*mace_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);*/ + mace_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc); config_found(self, &pba, macepci_print); #endif @@ -220,9 +241,6 @@ else aprint_normal(" bus %d", pba->pba_bus); - /* Mega XXX */ - *(volatile u_int32_t *)0xb4000034 = 0; /* prime timer */ - return UNCONF; } @@ -234,19 +252,9 @@ { pcireg_t data; - /* This should be handled by a real interrupt handler */ - if ((*(volatile u_int32_t *)0xbf080004 & ~0x00100000) != 6) - panic("pcierr: %x %x", *(volatile u_int32_t *)0xbf080000, - *(volatile u_int32_t *)0xbf080004); - - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = tag | reg; - data = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cfc); - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = 0; - - if (*(volatile u_int32_t *)0xbf080004 & 0xf0000000) { - *(volatile u_int32_t *)0xbf080004 = 0; - return (pcireg_t)-1; - } + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); + data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); return data; } @@ -262,9 +270,9 @@ if (tag == 0) return; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = tag | reg; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cfc) = data; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8) = 0; + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg)); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data); + bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0); } @@ -275,7 +283,88 @@ macepci_intr(arg) void *arg; { - printf("macepci_intr!\n"); + struct macepci_softc *sc = (struct macepci_softc *)arg; + pci_chipset_tag_t pc = &sc->sc_pc; + u_int32_t error, address; + + error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS); + address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR); + while (error & 0xffc00000) { + if (error & MACE_PERR_MASTER_ABORT) { + /* + * this seems to be a more-or-less normal error + * condition (e.g., "pcictl pci0 list" generates + * a _lot_ of these errors, so no message for now + * while I figure out if I missed a trick somewhere. + */ + error &= ~MACE_PERR_MASTER_ABORT; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_TARGET_ABORT) { + printf("mace: target abort at %x\n", address); + error &= ~MACE_PERR_TARGET_ABORT; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_DATA_PARITY_ERR) { + printf("mace: parity error at %x\n", address); + error &= ~MACE_PERR_DATA_PARITY_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_RETRY_ERR) { + printf("mace: retry error at %x\n", address); + error &= ~MACE_PERR_RETRY_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_ILLEGAL_CMD) { + printf("mace: illegal command at %x\n", address); + error &= ~MACE_PERR_ILLEGAL_CMD; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_SYSTEM_ERR) { + printf("mace: system error at %x\n", address); + error &= ~MACE_PERR_SYSTEM_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_INTERRUPT_TEST) { + printf("mace: interrupt test at %x\n", address); + error &= ~MACE_PERR_INTERRUPT_TEST; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_PARITY_ERR) { + printf("mace: parity error at %x\n", address); + error &= ~MACE_PERR_PARITY_ERR; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_RSVD) { + printf("mace: reserved condition at %x\n", address); + error &= ~MACE_PERR_RSVD; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + + if (error & MACE_PERR_OVERRUN) { + printf("mace: overrun at %x\n", address); + error &= ~MACE_PERR_OVERRUN; + bus_space_write_4(pc->iot, pc->ioh, + MACE_PCI_ERROR_FLAGS, error); + } + } return 0; } @@ -283,50 +372,50 @@ void pciaddr_resource_manage(pc, tag, func, ctx) - pci_chipset_tag_t pc; - pcitag_t tag; - pciaddr_resource_manage_func_t func; - void *ctx; + pci_chipset_tag_t pc; + pcitag_t tag; + pciaddr_resource_manage_func_t func; + void *ctx; { - pcireg_t val, mask; - bus_addr_t addr; - bus_size_t size; - int error, mapreg, type, reg_start, reg_end, width; - - val = macepci_conf_read(pc, tag, PCI_BHLC_REG); - switch (PCI_HDRTYPE_TYPE(val)) { - default: - printf("WARNING: unknown PCI device header."); - pciaddr.nbogus++; - return; - case 0: - reg_start = PCI_MAPREG_START; - reg_end = PCI_MAPREG_END; - break; - case 1: /* PCI-PCI bridge */ - reg_start = PCI_MAPREG_START; - reg_end = PCI_MAPREG_PPB_END; - break; - case 2: /* PCI-CardBus bridge */ - reg_start = PCI_MAPREG_START; - reg_end = PCI_MAPREG_PCB_END; - break; - } - error = 0; - - for (mapreg = reg_start; mapreg < reg_end; mapreg += width) { - /* inquire PCI device bus space requirement */ - val = macepci_conf_read(pc, tag, mapreg); - macepci_conf_write(pc, tag, mapreg, ~0); - - mask = macepci_conf_read(pc, tag, mapreg); - macepci_conf_write(pc, tag, mapreg, val); - - type = PCI_MAPREG_TYPE(val); - width = 4; + pcireg_t val, mask; + bus_addr_t addr; + bus_size_t size; + int error, mapreg, type, reg_start, reg_end, width; + + val = macepci_conf_read(pc, tag, PCI_BHLC_REG); + switch (PCI_HDRTYPE_TYPE(val)) { + default: + printf("WARNING: unknown PCI device header."); + pciaddr.nbogus++; + return; + case 0: + reg_start = PCI_MAPREG_START; + reg_end = PCI_MAPREG_END; + break; + case 1: /* PCI-PCI bridge */ + reg_start = PCI_MAPREG_START; + reg_end = PCI_MAPREG_PPB_END; + break; + case 2: /* PCI-CardBus bridge */ + reg_start = PCI_MAPREG_START; + reg_end = PCI_MAPREG_PCB_END; + break; + } + error = 0; + + for (mapreg = reg_start; mapreg < reg_end; mapreg += width) { + /* inquire PCI device bus space requirement */ + val = macepci_conf_read(pc, tag, mapreg); + macepci_conf_write(pc, tag, mapreg, ~0); - if (type == PCI_MAPREG_TYPE_MEM) { - size = PCI_MAPREG_MEM_SIZE(mask); + mask = macepci_conf_read(pc, tag, mapreg); + macepci_conf_write(pc, tag, mapreg, val); + + type = PCI_MAPREG_TYPE(val); + width = 4; + + if (type == PCI_MAPREG_TYPE_MEM) { + size = PCI_MAPREG_MEM_SIZE(mask); /* * XXXrkb: for MEM64 BARs, to be totally kosher @@ -348,8 +437,8 @@ * which we're not prepared to deal with, so I don't * feel bad punting on it... */ - if (PCI_MAPREG_MEM_TYPE(val) == - PCI_MAPREG_MEM_TYPE_64BIT) { + if (PCI_MAPREG_MEM_TYPE(val) == + PCI_MAPREG_MEM_TYPE_64BIT) { /* * XXX We could examine the upper 32 bits * XXX of the BAR here, but we are totally @@ -364,72 +453,74 @@ width = 8; if (size != 0) - macepci_conf_write(pc, tag, - mapreg + 4, 0); - } + macepci_conf_write(pc, tag, + mapreg + 4, 0); + } } else { - /* - * Upper 16 bits must be one. Devices may hardwire - * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. - */ - mask |= 0xffff0000; - size = PCI_MAPREG_IO_SIZE(mask); - } + /* + * Upper 16 bits must be one. Devices may hardwire + * them to zero, though, per PCI 2.2, 6.2.5.1, p 203. + */ + mask |= 0xffff0000; + size = PCI_MAPREG_IO_SIZE(mask); + } + + if (size == 0) /* unused register */ + continue; - if (size == 0) /* unused register */ - continue; + addr = pciaddr_ioaddr(val); - addr = pciaddr_ioaddr(val); - - /* reservation/allocation phase */ - error += pciaddr_do_resource_allocate (pc, tag, mapreg, - ctx, type, &addr, size); - -/* PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x", - mapreg, type ? "port" : "mem ", - (unsigned int)addr, (unsigned int)size)); */ + /* reservation/allocation phase */ + error += pciaddr_do_resource_allocate(pc, tag, mapreg, + ctx, type, &addr, size); + +#if 0 + PCIBIOS_PRINTV(("\n\t%02xh %s 0x%08x 0x%08x", + mapreg, type ? "port" : "mem ", + (unsigned int)addr, (unsigned int)size)); +#endif } - /* enable/disable PCI device */ - val = macepci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); + /* enable/disable PCI device */ + val = macepci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); - if (error == 0) - val |= (PCI_COMMAND_IO_ENABLE | + if (error == 0) + val |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | - PCI_COMMAND_MASTER_ENABLE | + PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_SPECIAL_ENABLE | - PCI_COMMAND_INVALIDATE_ENABLE | + PCI_COMMAND_INVALIDATE_ENABLE | PCI_COMMAND_PARITY_ENABLE); - else - val &= ~(PCI_COMMAND_IO_ENABLE | + else + val &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE); - macepci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val); - - if (error) - pciaddr.nbogus++; + macepci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, val); + if (error) + pciaddr.nbogus++; } bus_addr_t pciaddr_ioaddr(val) - u_int32_t val; + u_int32_t val; { - return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) - ? PCI_MAPREG_MEM_ADDR(val) - : PCI_MAPREG_IO_ADDR(val)); + + return ((PCI_MAPREG_TYPE(val) == PCI_MAPREG_TYPE_MEM) ? + PCI_MAPREG_MEM_ADDR(val) : PCI_MAPREG_IO_ADDR(val)); } int pciaddr_do_resource_allocate(pc, tag, mapreg, ctx, type, addr, size) - pci_chipset_tag_t pc; - pcitag_t tag; - void *ctx; - int mapreg, type; - bus_addr_t *addr; - bus_size_t size; + pci_chipset_tag_t pc; + pcitag_t tag; + void *ctx; + int mapreg, type; + bus_addr_t *addr; + bus_size_t size; { + switch (type) { case PCI_MAPREG_TYPE_IO: *addr = ioaddr_base; @@ -443,47 +534,43 @@ default: PCIBIOS_PRINTV(("attempt to remap unknown region (addr 0x%lx, " - "size 0x%lx, type %d)\n", *addr, size, type)); + "size 0x%lx, type %d)\n", *addr, size, type)); return 0; } - /* write new address to PCI device configuration header */ - macepci_conf_write(pc, tag, mapreg, *addr); + /* write new address to PCI device configuration header */ + macepci_conf_write(pc, tag, mapreg, *addr); /* check */ -#ifdef PCIBIOSVERBOSE - if (!pcibiosverbose) -#endif - { - printf("pci_addr_fixup: "); - pciaddr_print_devid(pc, tag); - } - if (pciaddr_ioaddr(macepci_conf_read(pc, tag, mapreg)) != *addr) { - macepci_conf_write(pc, tag, mapreg, 0); /* clear */ - printf("fixup failed. (new address=%#x)\n", (unsigned)*addr); - return (1); - } -#ifdef PCIBIOSVERBOSE - if (!pcibiosverbose) -#endif - printf("new address 0x%08x (size 0x%x)\n", (unsigned)*addr, - (unsigned)size); - return (0); + aprint_debug("pci_addr_fixup: "); + pciaddr_print_devid(pc, tag); + + if (pciaddr_ioaddr(macepci_conf_read(pc, tag, mapreg)) != *addr) { + macepci_conf_write(pc, tag, mapreg, 0); /* clear */ + aprint_normal("fixup failed. (new address=%#x)\n", + (unsigned)*addr); + return (1); + } + + aprint_debug("new address 0x%08x (size 0x%x)\n", + (unsigned)*addr, (unsigned)size); + + return (0); } void pciaddr_print_devid(pc, tag) - pci_chipset_tag_t pc; - pcitag_t tag; + pci_chipset_tag_t pc; + pcitag_t tag; { - int bus, device, function; - pcireg_t id; - - id = macepci_conf_read(pc, tag, PCI_ID_REG); - pci_decompose_tag(pc, tag, &bus, &device, &function); - printf("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function, - PCI_VENDOR(id), PCI_PRODUCT(id)); + int bus, device, function; + pcireg_t id; + + id = macepci_conf_read(pc, tag, PCI_ID_REG); + pci_decompose_tag(pc, tag, &bus, &device, &function); + aprint_debug("%03d:%02d:%d 0x%04x 0x%04x ", bus, device, function, + PCI_VENDOR(id), PCI_PRODUCT(id)); } diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/pci/pci_machdep.c ./pci/pci_machdep.c --- /cvs/netbsd/src/sys/arch/sgimips/pci/pci_machdep.c 2003-08-01 01:51:55.000000000 +0900 +++ ./pci/pci_machdep.c 2003-09-28 22:23:29.000000000 +0900 @@ -52,6 +52,8 @@ #include #include +#include + /* * PCI doesn't have any special needs; just use * the generic versions of these functions. @@ -87,7 +89,10 @@ pci_chipset_tag_t pc; int busno; { - return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */ + if (busno == 0) + return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */ + else + return 0; /* XXX */ } pcitag_t @@ -195,8 +200,6 @@ return NULL; } -extern void * crime_intr_establish(int, int, int, int (*)(void *), void *); - void * pci_intr_establish(pc, ih, level, func, arg) pci_chipset_tag_t pc; @@ -204,6 +207,7 @@ int level, (*func)(void *); void *arg; { + return crime_intr_establish(ih, 0, 0, func, arg); } @@ -212,7 +216,6 @@ pci_chipset_tag_t pc; void *cookie; { - panic("pci_intr_disestablish: not implemented"); - return; + panic("pci_intr_disestablish: not implemented"); } diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/sgimips/autoconf.c ./sgimips/autoconf.c --- /cvs/netbsd/src/sys/arch/sgimips/sgimips/autoconf.c 2003-08-01 01:51:56.000000000 +0900 +++ ./sgimips/autoconf.c 2003-09-28 20:38:59.000000000 +0900 @@ -83,24 +83,6 @@ printf("biomask %02x netmask %02x ttymask %02x clockmask %02x\n", biomask >> 8, netmask >> 8, ttymask >> 8, clockmask >> 8); - /* XXXrkb: hack until we get interrupt setup code right */ - if (mach_type == MACH_SGI_IP32) { - u_int64_t mask; - - mask = *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK); - aprint_debug("MACE_ISA_MASK was %llx\n", mask); - mask |= ((1UL << 20) | (1UL << 26)); - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK) = mask; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(MACE_PCI_FLUSH_W) = 0xffffffff; - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK) = 0x30ff10ULL; - - aprint_debug("CRM_MASK: %llx, MACEISA_MASK (%x) %llx\n", - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_INTMASK), - MACE_ISA_INT_MASK, - *(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_ISA_INT_MASK)); - - } - _splnone(); } @@ -243,7 +225,7 @@ /* * Check if netboot device. */ - if (netboot && strcmp(name, "sq") == 0) { + if (netboot && (strcmp(name, "sq") || strcmp(name, "mec")) == 0) { /* XXX Check unit number? (Which we don't parse yet) */ booted_device = dev; found = 1; diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/sgimips/console.c ./sgimips/console.c --- /cvs/netbsd/src/sys/arch/sgimips/sgimips/console.c 2003-08-01 01:51:56.000000000 +0900 +++ ./sgimips/console.c 2003-09-28 21:42:57.000000000 +0900 @@ -80,8 +80,10 @@ speed = strtoul(dbaud, NULL, 10); -#if (defined(IP20) || defined(IP22)) && (NZSC > 0) - if (mach_type == MACH_SGI_IP20 || mach_type == MACH_SGI_IP22) { +#if (defined(IP20) || defined(IP22) || defined(IP28)) && (NZSC > 0) + if (mach_type == MACH_SGI_IP20 || + mach_type == MACH_SGI_IP22 || + mach_type == MACH_SGI_IP28) { if (strlen(consdev) == 9 && strncmp(consdev, "serial", 6) == 0 && (consdev[7] == '0' || consdev[7] == '1')) { @@ -90,7 +92,7 @@ return; } } -#endif /* (IP20 || IP22) && (NZSC > 0) */ +#endif /* (IP20 || IP22 || IP28) && (NZSC > 0) */ #if defined(IP32) && (NCOM > 0) if (mach_type == MACH_SGI_IP32) { @@ -99,14 +101,15 @@ (consdev[7] == '0' || consdev[7] == '1')) { /* XXX: hardcoded MACE iotag */ if (comcnattach(3, ((consdev[7] == '0') ? - MIPS_PHYS_TO_KSEG1(MACE_ISA_SER1_BASE) : - MIPS_PHYS_TO_KSEG1(MACE_ISA_SER2_BASE)), + MIPS_PHYS_TO_KSEG1(0x1f390000) : + MIPS_PHYS_TO_KSEG1(0x1f380000)), speed, COM_FREQ, COM_TYPE_NORMAL, comcnmode) == 0) return; - printf("can't init serial hardware console!\n"); + panic("can't init serial hardware console!"); } + panic("ip32 supports serial console only. sorry."); } #endif /* IP32 && (NCOM > 0) */ @@ -125,10 +128,12 @@ KGDB_DEVMODE); # endif /* IP32 && (NCOM > 0) */ -# if (defined(IP20) || defined(IP22)) && (NZSC > 0) - if (mach_type == MACH_SGI_IP20 || mach_type == MACH_SGI_IP22) +# if (defined(IP20) || defined(IP22) || defined(IP28)) && (NZSC > 0) + if (mach_type == MACH_SGI_IP20 || + mach_type == MACH_SGI_IP22 || + mach_type == MACH_SGI_IP28) zs_kgdb_init(); /* XXX */ -# endif /* (IP20 || IP22) && (NZSC > 0) */ +# endif /* (IP20 || IP22 || IP28) && (NZSC > 0) */ } #endif /* KGDB */ diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/sgimips/cpu.c ./sgimips/cpu.c --- /cvs/netbsd/src/sys/arch/sgimips/sgimips/cpu.c 2003-08-01 01:51:56.000000000 +0900 +++ ./sgimips/cpu.c 2003-09-28 20:38:59.000000000 +0900 @@ -73,11 +73,4 @@ { printf(": "); cpu_identify(); - -#ifdef IP22 - if (mach_type == MACH_SGI_IP22) { /* XXX Indy */ - extern void ip22_cache_init(struct device *); - ip22_cache_init(self); - } -#endif } diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/sgimips/ip22.c ./sgimips/ip22.c --- /cvs/netbsd/src/sys/arch/sgimips/sgimips/ip22.c 2003-08-01 01:51:56.000000000 +0900 +++ ./sgimips/ip22.c 2003-09-28 20:38:59.000000000 +0900 @@ -50,6 +50,7 @@ u_int32_t next_clk_intr; u_int32_t missed_clk_intrs; static unsigned long last_clk_intr; +u_int32_t int23addr; static struct evcnt mips_int5_evcnt = EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "mips", "int 5 (clock)"); @@ -81,7 +82,6 @@ { u_int i; u_int32_t sysid; - u_int32_t int23addr; unsigned long cps; unsigned long ctrdiff[3]; @@ -277,14 +277,8 @@ int intnum; u_int32_t mstat; u_int32_t mmask; - u_int32_t int23addr; int which = (int)arg; - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; - ret = 0; mstat = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x10); mmask = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x14 + @@ -314,12 +308,6 @@ int ret; u_int32_t l0stat; u_int32_t l0mask; - u_int32_t int23addr; - - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; ret = 0; l0stat = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x00); @@ -346,12 +334,6 @@ int ret; u_int32_t l1stat; u_int32_t l1mask; - u_int32_t int23addr; - - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; l1stat = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x08); l1mask = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x0c); @@ -381,7 +363,6 @@ void *arg; { u_int32_t mask; - u_int32_t int23addr; if (level < 0 || level >= NINTR) panic("invalid interrupt level"); @@ -392,11 +373,6 @@ intrtab[level].ih_fun = handler; intrtab[level].ih_arg = arg; - if (mach_subtype == MACH_SGI_IP22_FULLHOUSE) - int23addr = 0x1fbd9000; - else - int23addr = 0x1fbd9880; - if (level < 8) { mask = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(int23addr + 0x4); mask |= (1 << level); @@ -479,32 +455,4 @@ return (endctr - startctr) / roundtime * roundtime; } -void ip22_cache_init(struct device *); - -void -ip22_cache_init(struct device *self) -{ - - /* - * If we don't have an R4000-style cache, then initialize the - * IP22 SysAD L2 cache. - * - * XXX: For now we disable the SysAD cache on R4600/R5k systems, - * as there's no code to drive it; also make sure to clear the - * flags used by the generic MIPS code so it doesn't attempt to - * use the L2. - */ - switch (MIPS_PRID_IMPL(cpu_id)) { - case MIPS_R4600: -#ifndef ENABLE_MIPS_R3NKK - case MIPS_R5000: -#endif - mips_sdcache_size = 0; - mips_sdcache_line_size = 0; - printf("%s: disabling IP22 SysAD L2 cache\n", self->dv_xname); - ip22_sdcache_disable(); - break; - } -} - #endif /* IP22 */ diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/sgimips/ip32.c ./sgimips/ip32.c --- /cvs/netbsd/src/sys/arch/sgimips/sgimips/ip32.c 2003-08-01 01:51:56.000000000 +0900 +++ ./sgimips/ip32.c 2003-09-28 22:22:01.000000000 +0900 @@ -3,7 +3,7 @@ /* * Copyright (c) 2000 Soren S. Jorvang * Copyright (c) 2001, 2002 Rafal K. Boni - * Copyright (c) 2002 Christopher Sekiya + * Copyright (c) 2002, 2003 Christopher Sekiya * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -53,7 +53,8 @@ #include #include -#include +#include +#include void ip32_init(void); void ip32_bus_reset(void); @@ -61,10 +62,6 @@ void ip32_intr_establish(int, int, int (*)(void *), void *); unsigned long ip32_clkread(void); -void crime_intr(u_int); -void *crime_intr_establish(int, int, int, int (*)(void *), void *); -void mace_intr(u_int); - u_int32_t next_clk_intr; u_int32_t missed_clk_intrs; static unsigned long last_clk_intr; @@ -84,6 +81,9 @@ u_int64_t baseline; u_int32_t cps; + /* XXX nasty hack */ + bus_space_handle_t ioh = MIPS_PHYS_TO_KSEG1(0x14000000); + /* * NB: don't enable watchdog here as we do on IP22, since the * fixed -- and overly short -- duration of the IP32 watchdog @@ -95,15 +95,14 @@ */ /* Reset CRIME CPU & memory error registers */ - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CPU_ERROR_STAT) = 0; - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_STAT) = 0; + bus_space_write_8(iot, ioh, CRIME_CPU_ERROR_STAT, 0); + bus_space_write_8(iot, ioh, CRIME_MEM_ERROR_STAT, 0); #define WAIT_MS 50 - baseline = *(volatile u_int64_t *) - MIPS_PHYS_TO_KSEG1(CRIME_TIME) & CRIME_TIME_MASK; + baseline = bus_space_read_8(iot, ioh, CRIME_TIME) & CRIME_TIME_MASK; cps = mips3_cp0_count_read(); - while (((*(volatile u_int64_t *)MIPS_PHYS_TO_KSEG1(CRIME_TIME) + while ((( bus_space_read_8(iot, ioh, CRIME_TIME) & CRIME_TIME_MASK) - baseline) < WAIT_MS * 1000000 / 15) continue; cps = mips3_cp0_count_read() - cps; @@ -138,8 +137,11 @@ void ip32_bus_reset(void) { - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CPU_ERROR_STAT) = 0; - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_STAT) = 0; + + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CPU_ERROR_STAT, 0); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_MEM_ERROR_STAT, 0); } /* @@ -158,29 +160,9 @@ u_int64_t crime_intstat, crime_intmask, crime_ipending; /* enable watchdog timer, clear it */ - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) |= - CRIME_CONTROL_DOG_ENABLE; - *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG) = 0; - -#if 1 - /* - * XXXrkb: Even if this code makes sense (which I'm not sure of; - * the magic number of "6" seems to correspond to capability bits - * of the card/slot in question -- not 66 Mhz capable, fast B2B - * capable and a medium DEVSEL timing -- and also seem to corres- - * pond to on-reset values of this register), these errors should - * be dealt with in the MACE PCI interrupt, not here! - * - * The 0x00100000 is MACE_PERR_CONFIG_ADDR, so this code should - * panic on any other PCI errors except simple address errors on - * config. space accesses. This also seems wrong, but I lack the - * PCI clue to figure out how to deal with other error ATM... - */ - if ((*(volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS) & ~0x00100000) != 6) - panic("pcierr: %x %x", - *(volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_ADDR), - *(volatile u_int32_t *) MIPS_PHYS_TO_KSEG1(MACE_PCI_ERROR_FLAGS)); -#endif + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, CRIME_CONTROL_DOG_ENABLE); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, CRIME_WATCHDOG, 0); if (ipending & MIPS_INT_MASK_5) { last_clk_intr = mips3_cp0_count_read(); @@ -209,8 +191,10 @@ } if (ipending & MIPS_INT_MASK_0) { - crime_intmask = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_INTMASK); - crime_intstat = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_INTSTAT); + crime_intmask = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_INTMASK); + crime_intstat = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_INTSTAT); crime_ipending = (crime_intstat & crime_intmask); @@ -225,15 +209,25 @@ * CRIME interrupts for CPU and memory errors */ if (crime_ipending & CRIME_INT_MEMERR) { - u_int64_t address = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_ADDR); - u_int64_t status = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_MEM_ERROR_STAT); - printf("crime: memory error address %llx status %llx\n", address << 2, status); + u_int64_t address = + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_MEM_ERROR_ADDR); + u_int64_t status = + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_MEM_ERROR_STAT); + printf("crime: memory error address %llx" + " status %llx\n", address << 2, status); ip32_bus_reset(); } if (crime_ipending & CRIME_INT_CRMERR) { - u_int64_t stat = *(volatile u_int64_t *) MIPS_PHYS_TO_KSEG1(CRIME_CPU_ERROR_STAT); - printf("crime: cpu error %llx\n", stat); + u_int64_t stat = + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_CPU_ERROR_STAT); + printf("crime: cpu error %llx at" + " address %llx\n", stat, + bus_space_read_8(crime_sc->iot, + crime_sc->ioh, CRIME_CPU_ERROR_ADDR)); ip32_bus_reset(); } } diff -urN --exclude=CVS --exclude=obj.sgimips --exclude=compile /cvs/netbsd/src/sys/arch/sgimips/sgimips/machdep.c ./sgimips/machdep.c --- /cvs/netbsd/src/sys/arch/sgimips/sgimips/machdep.c 2003-09-28 16:41:13.000000000 +0900 +++ ./sgimips/machdep.c 2003-09-28 22:06:34.000000000 +0900 @@ -1,4 +1,4 @@ -/* $NetBSD: machdep.c,v 1.56 2003/09/15 06:39:22 simonb Exp $ */ +/* $NetBSD: machdep.c,v 1.57 2003/09/28 13:02:18 tsutsui Exp $ */ /* * Copyright (c) 2000 Soren S. Jorvang @@ -34,7 +34,7 @@ */ #include -__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.56 2003/09/15 06:39:22 simonb Exp $"); +__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.57 2003/09/28 13:02:18 tsutsui Exp $"); #include "opt_ddb.h" #include "opt_kgdb.h" @@ -77,14 +77,18 @@ #include #include -#if 0 #include +#if 0 +#include #endif #include #include +#if defined(IP32) #include +#include +#endif #include "ksyms.h" @@ -102,6 +106,9 @@ /* For sysctl_hw. */ extern char cpu_model[]; +#if 0 +extern int flush_pcache_anyway; +#endif struct sgimips_intrhand intrtab[NINTR]; @@ -142,8 +149,10 @@ void ip20_init(void); #endif -#ifdef IP22 +#if defined(IP22) || defined(IP28) void ip22_init(void); +extern void ip22_sdcache_disable(void); +extern void ip22_sdcache_enable(void); #endif #ifdef IP32 @@ -218,11 +227,6 @@ int kernstartpfn, kernendpfn; int i, rv, nsym; -#if 0 - /* Clear the BSS segment. XXX Is this really necessary? */ - memset(_edata, 0, _end - _edata); -#endif - /* * Initialize ARCS. This will set up the bootstrap console. */ @@ -395,7 +399,8 @@ break; case MACH_SGI_IP22: -#ifdef IP22 + case MACH_SGI_IP28: +#if defined(IP22) || defined(IP28) ip22_init(); #else unconfigured_system_type(mach_type); @@ -620,7 +625,7 @@ * and usually occupy more virtual memory than physical. */ size = MAXBSIZE * nbuf; - if (uvm_map(kernel_map, (vaddr_t *)&buffers, round_page(size), + if (uvm_map(kernel_map, (vaddr_t *)(void *)&buffers, round_page(size), NULL, UVM_UNKNOWN_OFFSET, 0, UVM_MAPFLAG(UVM_PROT_NONE, UVM_PROT_NONE, UVM_INH_NONE, UVM_ADV_NORMAL, 0)) != 0) @@ -693,6 +698,9 @@ int howto; char *bootstr; { +#if defined(IP32) + u_int64_t scratch; +#endif /* Take a snapshot before clobbering any registers. */ if (curlwp) savectx((struct user *)curpcb); @@ -718,21 +726,25 @@ resettodr(); } -#if 1 /* Clear and disable watchdog timer. */ switch (mach_type) { case MACH_SGI_IP22: + case MACH_SGI_IP28: *(volatile u_int32_t *)0xbfa00014 = 0; *(volatile u_int32_t *)0xbfa00004 &= ~0x100; break; +#if defined(IP32) case MACH_SGI_IP32: - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG) = 0; - *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) - &= ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_WATCHDOG, 0); + scratch = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL) & ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, scratch); break; - } #endif + } splhigh(); @@ -917,38 +929,47 @@ void ddb_trap_hook(int where) { +#if defined(IP32) + u_int64_t scratch; +#endif switch (where) { case 1: /* Entry to DDB, turn watchdog off */ switch (mach_type) { case MACH_SGI_IP22: + case MACH_SGI_IP28: *(volatile u_int32_t *)0xbfa00014 = 0; *(volatile u_int32_t *)0xbfa00004 &= ~0x100; break; - +#if defined(IP32) case MACH_SGI_IP32: - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG)= 0; - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) \ - &= ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_WATCHDOG, 0); + scratch = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL) & ~CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, scratch); break; +#endif } break; case 0: /* Exit from DDB, turn watchdog back on */ switch (mach_type) { case MACH_SGI_IP22: + case MACH_SGI_IP28: *(volatile u_int32_t *)0xbfa00004 |= 0x100; *(volatile u_int32_t *)0xbfa00014 = 0; break; - +#if defined(IP32) case MACH_SGI_IP32: - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_CONTROL) \ - |= CRIME_CONTROL_DOG_ENABLE; - *(volatile u_int32_t *) - MIPS_PHYS_TO_KSEG1(CRIME_WATCHDOG) = 0; + scratch = bus_space_read_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL) | CRIME_CONTROL_DOG_ENABLE; + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_CONTROL, scratch); + bus_space_write_8(crime_sc->iot, crime_sc->ioh, + CRIME_WATCHDOG, 0); break; +#endif } break; } @@ -960,33 +981,47 @@ { volatile u_int32_t cpu_config; - if (mach_type == MACH_SGI_IP32) - { -#if 1 - /* L2 cache does not work on IP32 (yet) */ - mips_sdcache_size = 0; - mips_sdcache_line_size = 0; - - cpu_config = mips3_cp0_config_read(); - cpu_config &= ~MIPS3_CONFIG_SE; - mips3_cp0_config_write(cpu_config); -#else - arcbios_tree_walk(mips_machdep_find_l2cache, NULL); - - cpu_config = mips3_cp0_config_read(); - printf("\nbefore mips_machdep_cache_config: SE = %x\n", - cpu_config & MIPS3_CONFIG_SE); - - r5k_enable_sdcache(); + arcbios_tree_walk(mips_machdep_find_l2cache, NULL); + switch (MIPS_PRID_IMPL(cpu_id)) { + case MIPS_R4600: + /* + * r4600 is on Indy-class machines only. Disable and + * flush pcache. + */ +#if defined(IP22) + mips_sdcache_size = 0; + mips_sdcache_line_size = 0; + ip22_sdcache_disable(); +#if 0 + flush_pcache_anyway = 1; +#endif +#endif + break; + case MIPS_R5000: cpu_config = mips3_cp0_config_read(); - printf("after mips_machdep_cache_config: SE = %x\n", - cpu_config & MIPS3_CONFIG_SE); + if (cpu_config & MIPS3_CONFIG_SC) { /* 1 = not present */ + mips_sdcache_size = 0; + mips_sdcache_line_size = 0; + + cpu_config = mips3_cp0_config_read(); + cpu_config &= ~MIPS3_CONFIG_SE; + mips3_cp0_config_write(cpu_config); + } else + r5k_enable_sdcache(); +#if 0 + flush_pcache_anyway = 1; #endif - } - else /* IP22 works, maybe */ - { - arcbios_tree_walk(mips_machdep_find_l2cache, NULL); + break; +#if 0 + case MIPS_R10000: + cpu_config = mips3_cp0_config_read(); + printf("\nr10k cpu config is %x\n", cpu_config); + break; +#endif + default: + printf("Don't know how to configure SC on this platform.\n"); + break; } }