Index: arch/mips/include/cache_r5k.h
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/include/cache_r5k.h,v
retrieving revision 1.1
diff -u -r1.1 cache_r5k.h
--- arch/mips/include/cache_r5k.h	8 Mar 2003 04:43:26 -0000	1.1
+++ arch/mips/include/cache_r5k.h	4 Oct 2003 14:41:49 -0000
@@ -64,7 +64,7 @@
 
 void	r5k_sdcache_wbinv_all(void);
 void	r5k_sdcache_wbinv_range(vaddr_t, vsize_t);
-void	r5k_sdcache_wbinv_rangeall(vaddr_t, vsize_t);
+void	r5k_sdcache_wbinv_range_index(vaddr_t, vsize_t);
 void	r5k_sdcache_inv_range(vaddr_t, vsize_t);
 void	r5k_sdcache_wb_range(vaddr_t, vsize_t);
 
Index: arch/mips/mips/cache_r5k.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/cache_r5k.c,v
retrieving revision 1.9
diff -u -r1.9 cache_r5k.c
--- arch/mips/mips/cache_r5k.c	15 Jul 2003 02:43:37 -0000	1.9
+++ arch/mips/mips/cache_r5k.c	4 Oct 2003 14:41:50 -0000
@@ -603,20 +603,22 @@
 void
 r5k_sdcache_wbinv_all(void)
 {
-	vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
-	vaddr_t eva = va + mips_sdcache_size;
 
-	while (va < eva) {
-		cache_op_r4k_line(va, R5K_Page_Invalidate_S);
-		va += (128 * 32);
-	}
+	r5k_sdcache_wbinv_range(MIPS_PHYS_TO_KSEG0(0), mips_sdcache_size);
 }
 
-/* XXX: want wbinv_range_index here instead? */
 void
-r5k_sdcache_wbinv_rangeall(vaddr_t va, vsize_t size)
+r5k_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)
 {
-	r5k_sdcache_wbinv_all();
+
+	/*
+	 * Since we're doing Index ops, we expect to not be able
+	 * to access the address we've been given.  So, get the
+	 * bits that determine the cache index, and make a KSEG0
+	 * address out of them.
+	 */
+	va = MIPS_PHYS_TO_KSEG0(va & (mips_sdcache_size - 1));
+	r5k_sdcache_wbinv_range(va, size);
 }
 
 #define	round_page(x)		(((x) + (128 * 32 - 1)) & ~(128 * 32 - 1))
@@ -625,13 +627,30 @@
 void
 r5k_sdcache_wbinv_range(vaddr_t va, vsize_t size)
 {
+	uint32_t ostatus, taglo;
 	vaddr_t eva = round_page(va + size);
+
 	va = trunc_page(va);
 
+	__asm __volatile(
+		".set noreorder		\n\t"
+		".set noat		\n\t"
+		"mfc0 %0, $12		\n\t"
+		"mtc0 $0, $12		\n\t"
+		".set reorder		\n\t"
+		".set at"
+		: "=r"(ostatus));
+
+	__asm __volatile("mfc0 %0, $28" : "=r"(taglo));
+	__asm __volatile("mtc0 $0, $28");
+
 	while (va < eva) {
 		cache_op_r4k_line(va, R5K_Page_Invalidate_S);
 		va += (128 * 32);
 	}
+
+	__asm __volatile("mtc0 %0, $12; nop" :: "r"(ostatus));
+	__asm __volatile("mtc0 %0, $28; nop" :: "r"(taglo));
 }
 
 void
Index: arch/mips/mips/pmap.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/pmap.c,v
retrieving revision 1.150
diff -u -r1.150 pmap.c
--- arch/mips/mips/pmap.c	12 Sep 2003 15:29:16 -0000	1.150
+++ arch/mips/mips/pmap.c	4 Oct 2003 14:42:20 -0000
@@ -1580,7 +1580,7 @@
 
 	mips_pagezero((caddr_t)MIPS_PHYS_TO_KSEG0(phys));
 
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS)	/* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged WB cache,
 	 * and no L2 cache to warn of aliased mappings,	we must force a
@@ -1589,10 +1589,14 @@
 	 * might read old stale DRAM footprint, not the just-written data.
 	 *
 	 * XXXJRT This is totally disgusting.
+	 *
+	 * XXX This seems also needed for R4600/R5000
+	 * XXX (which have 2-way L1 cache) even with L2 cache?
 	 */
-	if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0)
+	if (MIPS_HAS_R4K_MMU &&
+	    (mips_sdcache_line_size == 0 || mips_pdcache_ways > 1))
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(phys), NBPG);
-#endif	/* MIPS3_PLUS && !MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 }
 
 /*
@@ -1613,7 +1617,7 @@
 		printf("pmap_copy_page(%lx) dst nonphys\n", (u_long)dst);
 #endif
 
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS)	/* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged cache,
 	 * and no L2 cache to warn of aliased mappings, we must force an
@@ -1627,17 +1631,18 @@
 	 * It would probably be better to map the destination as a
 	 * write-through no allocate to reduce cache thrash.
 	 */
-	if (MIPS_HAS_R4K_MMU && mips_sdcache_line_size == 0) {
+	if (MIPS_HAS_R4K_MMU &&
+	    (mips_sdcache_line_size == 0 || mips_pdcache_ways > 1)) {
 		/*XXX FIXME Not very sophisticated */
 		mips_flushcache_allpvh(src);
 /*		mips_flushcache_allpvh(dst); */
 	}
-#endif	/* MIPS3_PLUS && !MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 
 	mips_pagecopy((caddr_t)MIPS_PHYS_TO_KSEG0(dst),
 		      (caddr_t)MIPS_PHYS_TO_KSEG0(src));
 
-#if defined(MIPS3_PLUS) && defined(MIPS3_L2CACHE_ABSENT)	/* XXX mmu XXX */
+#if defined(MIPS3_PLUS)	/* XXX mmu XXX */
 	/*
 	 * If we have a virtually-indexed, physically-tagged WB cache,
 	 * and no L2 cache to warn of aliased mappings,	we must force a
@@ -1648,12 +1653,16 @@
 	 *      the destination as well?
 	 *
 	 * XXXJRT -- This is totally disgusting.
+	 *
+	 * XXX This seems also needed for R4600/R5000
+	 * XXX (which have 2-way L1 cache) even with L2 cache?
 	 */
-	if (MIPS_HAS_R4K_MMU) {
+	if (MIPS_HAS_R4K_MMU &&
+	    (mips_sdcache_line_size == 0 || mips_pdcache_ways > 1)) {
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(src), NBPG);
 		mips_dcache_wbinv_range(MIPS_PHYS_TO_KSEG0(dst), NBPG);
 	}
-#endif	/* MIPS3_PLUS && !MIPS3_L2CACHE_ABSENT */
+#endif	/* MIPS3_PLUS */
 }
 
 /*
--- arch/mips/mips/cache.c.0	2003-10-04 23:08:03.000000000 +0900
+++ arch/mips/mips/cache.c	2003-10-04 23:39:50.000000000 +0900
@@ -755,12 +755,13 @@
 	case MIPS_R5000:
 #endif
 	case MIPS_RM5200:
+		mips_sdcache_write_through = 1;
 		mips_cache_ops.mco_sdcache_wbinv_all =
 		    r5k_sdcache_wbinv_all;
 		mips_cache_ops.mco_sdcache_wbinv_range =
 		    r5k_sdcache_wbinv_range;
 		mips_cache_ops.mco_sdcache_wbinv_range_index =
-		    r5k_sdcache_wbinv_rangeall;	/* XXX? */
+		    r5k_sdcache_wbinv_range_index;
 		mips_cache_ops.mco_sdcache_inv_range =
 		    r5k_sdcache_wbinv_range;
 		mips_cache_ops.mco_sdcache_wb_range =
--- arch/sgimips/sgimips/machdep.c.orig	2003-10-04 23:33:10.000000000 +0900
+++ arch/sgimips/sgimips/machdep.c	2003-10-04 23:37:40.000000000 +0900
@@ -991,17 +991,13 @@
 #endif
 	case MIPS_R5000:
 		cpu_config = mips3_cp0_config_read();
-#if 1 /* disable r5ksc for now */
-		cpu_config &= ~MIPS3_CONFIG_SE;
-		mips3_cp0_config_write(cpu_config);
-#else
 		if ((cpu_config & MIPS3_CONFIG_SC) == 0)
 			r5k_enable_sdcache();
-		else
-#endif
-		{
+		else {
 			mips_sdcache_size = 0;
 			mips_sdcache_line_size = 0;
+			cpu_config &= ~MIPS3_CONFIG_SE;
+			mips3_cp0_config_write(cpu_config);
 		}
 		break;
 #ifdef ENABLE_MIPS4_CACHE_R10K